Exciting progress in the ALLEGRO project! Our silicon photonic switch layout has been finalized and successfully submitted for fabrication to Tower Semiconductor. 🎉

Key highlights of this achievement:
✅ Design Rule Check (DRC) Clean: Extensive efforts were made to resolve all DRC violations at both the building block and full-chip levels.
✅ Close Collaboration with TowerSemi: Continuous feedback and implementation of foundry recommendations ensured a smooth submission process.
✅ Enhanced Debugging Workflow: By integrating Calibre DRC rules into the Luceda IPKISS environment, we streamlined debugging and minimized errors when transferring design files.
✅ Optimized Metal Density: Advanced tiling strategies were applied across three metal layers to meet density requirements, with additional dummy tiles added for compliance.

This milestone marks a major step forward in the ALLEGRO project, funded under Horizon Europe . Looking forward to seeing this design come to life!

💡 Big thanks to the teams at NVIDIA, Tower Semiconductor, and all our partners for their dedication to pushing the boundaries of silicon photonics!

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